1. Field of the Invention
The present invention relates to a data transfer controlling apparatus for direct memory access (DMA), more particularly, to a DMA data transfer controlling apparatus which controls data transfer by a DMA controller controlling the data transfer without going through a CPU.
2. Description of the Related Art
In general, a DMA transfer controlling apparatus is comprised of a central processing unit (CPU), input-output unit (I/O unit), memories, and a DMA controller connected via address buses, data buses, and buses for control signals (for example, read/write signal buses) to form a microcomputer system. When DMA transfer is performed, the above-mentioned DMA controller takes over the above-mentioned buses from the CPU. In accordance with commands written in advance by the CPU into the DMA controller, the DMA controller controls the data transfer between the memories or between the memory and the I/O unit.
In this connection, it is conceived to apply microprogram control to the DMA controller. If the microprogram control is applied, the DMA controller may be comprised of a request handler, data handler, and microunit. Here, the microunit is a unit which, based on a data transfer request signal from the above-mentioned I/O unit, for example, sends out control signals for predetermined data transfer (that is, data transfer for a predetermined channel) to the data handler, etc. To carry out such an operation, the microunit is provided inside with a plurality of microaddress registers corresponding to the number of channels and a micro read only memory (.mu.ROM) which successively outputs predetermined microinstructions in accordance with microaddress information successively read out from one of the microaddress registers. The successively read out microinstructions (by which microinstructions are comprised a microprogram) are supplied to the above-mentioned data handler, etc. as control signals for data transfer for a corresponding channel.
In this case, after the data transfer program processing (comprised of a plurality of transfer cycles) for one channel (here, the first channel) is completed, the microunit receives a transfer request signal for processing of the data transfer program for another channel (here, the second channel). That is, the transfer request signal for processing of the data transfer program is received by the microunit at the final cycle of the transfer program processing for the above-mentioned first channel (that is, after the correct execution of the data transfer processing for the first channel), whereby the channel by which data is to be transferred is switched.
However, in this case, there is a deviation of one cycle between the timing by which microaddress information is read out from a predetermined microaddress register and the timing for execution of a predetermined data transfer cycle by the microinstruction output from the .mu.ROM in accordance with the read out microaddress information (that is, the timing of internal processing for transfer in the DMA controller is ahead of the timing of the external transfer cycle by one cycle). Therefore, when the transfer request signal is received at the above-mentioned timing, there is a dead cycle of one cycle length from the transfer cycle of the first channel (final transfer cycle before change of channels) until entering the transfer cycle of the second channel (first transfer cycle after change of channels), that is, for performing channel transition. As a result, if the microprogram control is simply applied to the DMA controller, there is the problem that this delays the operation of the apparatus.
To eliminate the above problem, it is conceived to send the above-mentioned transfer request signal to the microunit before the end of the processing of the transfer program of the first channel (that is, during the transfer cycle one cycle before the final transfer cycle) so as to prepare for the next transfer in advance in the microunit.
However, when the transfer request signal is received at this timing, if a bus error arises during the transfer with respect to the first channel and a bus error signal is sent in from the outside (the bus error signal being sent in at the final transfer cycle of the above-mentioned first channel), the channel for the next data transfer (that is, the above-mentioned second channel) will already be switched to by the receipt of the above-mentioned transfer request signal before that (in transfer cycle one cycle before final transfer cycle). As a result, there will be the mistaken judgment that the above-mentioned bus error has arisen in the data transfer of the above-mentioned second channel. Therefore, when a transfer program processing request is received at the above-mentioned timing, as mentioned above, despite the bus error having arisen in the data transfer of the first channel, there is the problem that the switching to the above-mentioned second channel before detection of this will lead to the erasure (destruction) of the microaddress information which is stored in the microaddress register of the second channel (that is, the microaddress information will be rewritten to the microaddress information for the bus error processing). Therefore, in the above DMA controller, it is impossible to output transfer program processing request signals in the transfer cycle before the final transfer cycle, as mentioned above.
Next, in the start processing of the above-mentioned transfer program, microaddress information may be read out as an initial value from a mapping program logic array (mapping PLA) provided in the microunit. Next, data of the .mu.ROM (microinstruction) is read out based on the readout microaddress information. Based on the read out microinstruction, a predetermined data transfer program processing is started via the above-mentioned data handler.
In this way, in the above DMA controller, when start processing for the transfer program is requested, microaddress information is read out as an initial value from the above-mentioned mapping PLA and then input into the .mu.ROM, so it took about two cycles from the input of the above-mentioned start processing request signal into the mapping PLA to the start of the above-mentioned data transfer processing. Thus, there is the problem that this reduced the speed of the above-mentioned start processing by a corresponding amount.